Reconfigurable Rf Power Amplifiers On Silicon For Wireless Handsets Analog Circuits And Signal Processing

Reconfigurable RF Power Amplifiers on Silicon for Wireless Handsets is intended to designers and researchers who have to tackle the efficiency/linearity trade-off in modern RF transmitters so as to extend their battery lifetime. High data rate 3G/4G standards feature broad channel bandwidths, high dynamic range and critical envelope variations which generally forces the power amplifier (PA) to operate in a low efficiency backed-off regime.

Classic efficiency enhancement techniques such as Envelope Elimination and Restoration reveal to be little compliant with handset-dedicated PA implementation due to their channel-bandwidth-limited behavior and their increased die area consumption and/or bill-of-material. The architectural advances that are proposed in this book circumvent these issues since they put the stress on low die-area /low power-consumption control circuitry.

The advantages of silicon over III/V technologies are highlighted by several analogue signal processing techniques that can be implemented on-chip with a power amplifier. System-level and transistor-level simulations are combined to illustrate the principles of the proposed power adaptive solutions.

Measurement on BICMOS demonstrators allows validating the functionality of dynamic linearity/efficiency management. In Reconfigurable RF Power Amplifiers on Silicon for Wireless Handsets, PA designers will find a review of technologies, architectures and theoretical formalisms (Volterra series) that are traditionally related to PA design.

Specific issues that one encounters in power amplifiers (such as thermal / memory effects, stability, VSWR sensitivity) and the way of overcoming them are also extensively considered throughout this book.